International Journal of

ADVANCED AND APPLIED SCIENCES

EISSN: 2313-3724, Print ISSN: 2313-626X

Frequency: 12
line decor
  
line decor

 Volume 10, Issue 9 (September 2023), Pages: 68-74

----------------------------------------------

 Original Research Paper

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

 Author(s): 

 Hammad H. Alshortan, Yasser Almalaq, Muhammad Imran Khan *

 Affiliation(s):

 Department of Electrical Engineering, College of Engineering, University of Hail, Hail, Saudi Arabia

  Full Text - PDF          XML

 * Corresponding Author. 

  Corresponding author's ORCID profile: https://orcid.org/0000-0002-7844-9567

 Digital Object Identifier: 

 https://doi.org/10.21833/ijaas.2023.09.008

 Abstract:

This research paper investigates the influence of different initial design techniques on the area, timing, and power aspects of technology-mapped designs. As a practical case study, we undertake the design and analysis of a 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, a fundamental component of all processors, comprises three major units: the Adder responsible for signed and unsigned number addition and subtraction, the Logic unit which handles bitwise logical operations, and the Shifter unit facilitates arithmetic and logical shift operations. The two adder designs are based on the ripple carry method (ALU_RCA) and the Sklansky method (ALU_SKL), respectively. The design and analysis process involved utilizing established toolsets from Cadence, including NCSIM for simulation and verification, RTL Compiler for logic synthesis, static timing analysis and power estimation, and SOC encounter tool for floorplanning and layout. Through this investigation, we aim to shed light on the varying performance implications of different initial design approaches in technology-mapped designs.

 © 2023 The Authors. Published by IASE.

 This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

 Keywords: Initial design techniques, Technology mapped designs, Arithmetic logic unit, Ripple carry method, Sklansky method

 Article History: Received 27 March 2023, Received in revised form 31 July 2023, Accepted 3 August 2023

 Acknowledgment 

This research has been funded by the Scientific Research Deanship at the University of Ha’il–Saudi Arabia through project number GR-22 106.”

 Compliance with ethical standards

 Conflict of interest: The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

 Citation:

 Alshortan HH, Almalaq Y, and Khan MI (2023). Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit. International Journal of Advanced and Applied Sciences, 10(9): 68-74

 Permanent Link to this page

 Figures

 Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 

 Tables

 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 

----------------------------------------------   

 References (34)

  1. Alrashdi A and Khan MI (2022). Design and comparative analysis of high speed and low power ALU using RCA and Sklansky adders for high-performance systems. Engineering, Technology and Applied Science Research, 12(2): 8426-8430. https://doi.org/10.48084/etasr.4817   [Google Scholar]
  2. Alshortan HH, Alogla A, Eleiwa MA, and Khan MI (2021). Low cost high gain 8×8 planar array antenna for 5G applications at 28GHz. Engineering, Technology and Applied Science Research, 11(6): 7964-7967. https://doi.org/10.48084/etasr.4609   [Google Scholar]
  3. Buzdar AR, Sun L, Azhar MW, Khan MI, and Rao K (2017a). Area and energy efficient Viterbi accelerator for embedded processor datapaths. International Journal of Advanced Computer Science and Applications, 8(3): 402-407. https://doi.org/10.14569/IJACSA.2017.080355   [Google Scholar]
  4. Buzdar AR, Sun L, Rao K, Azhar MW, and Khan MI (2017b). Cyclic redundancy checking (CRC) accelerator for embedded processor datapaths. International Journal of Advanced Computer Science and Applications, 8(2): 321-325. https://doi.org/10.14569/IJACSA.2017.080242   [Google Scholar]
  5. Choi Y and Swartzlander EE (2008). Speculative carry generation with prefix adder. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(3): 321-326. https://doi.org/10.1109/TVLSI.2007.915502   [Google Scholar]
  6. Dossis M (2015). High-level synthesis integrated verification. Engineering, Technology and Applied Science Research, 5(5): 864-870. https://doi.org/10.48084/etasr.596   [Google Scholar]
  7. Durrani YA, Riesgo T, Khan MI, and Mahmood T (2016). Power analysis approach and its application to IP-based SoC design. COMPEL-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, 35(3): 1218-1236. https://doi.org/10.1108/COMPEL-08-2015-0283   [Google Scholar]
  8. Gan Z, Salman E, and Stanaćević M (2015). Figures-of-merit to evaluate the significance of switching noise in analog circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(12): 2945-2956. https://doi.org/10.1109/TVLSI.2014.2386315   [Google Scholar]
  9. Han D (2013). Comparison of commonly used image interpolation methods. In the 2nd International Conference on Computer Science and Electronics Engineering, Atlantis Press, Hangzhou, China: 1556-1559. https://doi.org/10.2991/iccsee.2013.391   [Google Scholar]
  10. Huang D, Yang X, Chen H, Khan MI, and Lin F (2018). A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers. AEU-International Journal of Electronics and Communications, 84: 192-198. https://doi.org/10.1016/j.aeue.2017.12.003   [Google Scholar]
  11. Iannacci J (2021). The WEAF Mnecosystem: A perspective of MEMS/NEMS technologies as pillars of future 6G, tactile internet and super-IoT. Microsystem Technologies, 27: 4193–4207. https://doi.org/10.1007/s00542-021-05230-3   [Google Scholar]
  12. Jha AK, Kumar A, Schaefer G, and Ahad MAR (2014). An efficient edge preserving image interpolation algorithm. In the International Conference on Informatics, Electronics and Vision, IEEE, Dhaka, Bangladesh: 1-4. https://doi.org/10.1109/ICIEV.2014.6850820   [Google Scholar] PMCid:PMC3952416
  13. Khan MI (2023). Harmonic estimation and comparative analysis of ultra-high speed flip-flop and latch topologies for low power and high performance future generation micro-/nano electronic systems. ACM Transactions on Design Automation of Electronic Systems, 28(4): 1-17. https://doi.org/10.1145/3590770   [Google Scholar]
  14. Khan MI and Lin F (2014a). Impact of transistor model accuracy on harmonic spectra emitted by logic circuits. In the 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, IEEE, Guilin, China: 1-3. https://doi.org/10.1109/ICSICT.2014.7021316   [Google Scholar]
  15. Khan MI and Lin F (2014b). Comparative analysis and design of harmonic aware low-power latches and flip-flops. In the IEEE International Conference on Electron Devices and Solid-State Circuits, IEEE, Chengdu, China: 1-2. https://doi.org/10.1109/EDSSC.2014.7061282   [Google Scholar]
  16. Khan MI, Alshammari AS, Alshammari BM, and Alzamil AA (2021). Estimation and analysis of higher-order harmonics in advanced integrated circuits to implement noise-free future-generation micro-and nanoelectromechanical systems. Micromachines, 12(5): 541. https://doi.org/10.3390/mi12050541   [Google Scholar] PMid:34068549 PMCid:PMC8151574
  17. Khan MI, Dong H, Shabbir F, and Shoukat R (2018b). Embedded passive components in advanced 3D chips and micro/nano electronic systems. Microsystem Technologies, 24: 869-877. https://doi.org/10.1007/s00542-017-3586-3   [Google Scholar]
  18. Khan MI, Qamar A, Shabbir F, and Shoukat R (2017). Design, development and implementation of a low power and high speed pipeline A/D converter in submicron CMOS technology. Microsystem Technologies, 23: 6005-6014. https://doi.org/10.1007/s00542-017-3550-2   [Google Scholar]
  19. Khan MI, Shoukat R, Mukherjee K, and Dong H (2018a). Analysis of harmonic contents of switching waveforms emitted by the ultra-high speed digital CMOS integrated circuits for use in future micro/nano systems applications. Microsystem Technologies, 24: 1201-1206. https://doi.org/10.1007/s00542-017-3486-6   [Google Scholar]
  20. Li R, Yang Z, and Cai B (2023). Design and test of a linear micro-motion stage with adjustable stiffness and frequency. Microsystem Technologies, 29(3): 377-385. https://doi.org/10.1007/s00542-023-05433-w   [Google Scholar]
  21. Marculescu R, Marculescu D, and Pedram M (1998). Probabilistic modeling of dependencies during switching activity analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(2): 73-83. https://doi.org/10.1109/43.681258   [Google Scholar]
  22. Markov IL, Hu J, and Kim MC (2015). Progress and challenges in VLSI placement research. In Proceedings of the IEEE, 103(11):1985–2003. https://doi.org/10.1109/JPROC.2015.2478963   [Google Scholar]
  23. Merkel C (2018). Device solutions to scientific computing. Nature Electronics, 1(7): 382-383. https://doi.org/10.1038/s41928-018-0108-y   [Google Scholar]
  24. Nouaiti A, Saad A, Mesbahi A, Khafallah M, and Reddak M (2019). Design and test of a new three-phase multilevel inverter for PV system applications. Engineering, Technology and Applied Science Research, 9(1): 3846-3851. https://doi.org/10.48084/etasr.2573   [Google Scholar]
  25. O'Dare MJ and Arslan T (1994). Generating test patterns for VLSI circuits using a genetic algorithm. Electronics Letters, 30(10): 778-779. https://doi.org/10.1049/el:19940524   [Google Scholar]
  26. Pedroni VA (2020). Circuit design with VHDL. MIT Press, Cambridge, USA.   [Google Scholar]
  27. Salman E, Jakushokas R, Friedman EG, Secareanu RM, and Hartin OL (2009). Methodology for efficient substrate noise analysis in large-scale mixed-signal circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(10): 1405-1418. https://doi.org/10.1109/TVLSI.2008.2003518   [Google Scholar]
  28. Scheffer L, Lavagno L, and Martin G (2006). EDA for IC system design, verification, and testing. Taylor and Francis Group, Boca Raton, USA.   [Google Scholar]
  29. Shoukat R and Khan MI (2018a). Design and development of a clip building block system for MEMS. Microsystem Technologies, 24: 1025-1031. https://doi.org/10.1007/s00542-017-3453-2   [Google Scholar]
  30. Shoukat R and Khan MI (2018b). Nanotechnology based electrical control and navigation system for worm guidance using electric field gradient. Microsystem Technologies, 24: 989-993. https://doi.org/10.1007/s00542-017-3444-3   [Google Scholar]
  31. Simicic M, Weckx P, Parvais B, Roussel P, Kaczer B, and Gielen G (2018). Understanding the impact of time-dependent random variability on analog ICs: From single transistor measurements to circuit simulations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(3): 601-610. https://doi.org/10.1109/TVLSI.2018.2878841   [Google Scholar]
  32. Stojanovic V and Oklobdzija VG (1999). Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE Journal of Solid-State Circuits, 34(4): 536-548. https://doi.org/10.1109/4.753687   [Google Scholar]
  33. Tang M and Yao X (2007). A memetic algorithm for VLSI floorplanning. IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics), 37(1): 62-69. https://doi.org/10.1109/TSMCB.2006.883268   [Google Scholar] PMid:17278559
  34. Thomas S (2023). Chips that feel the heat. Nature Electronics, 6(3): 179-179. https://doi.org/10.1038/s41928-023-00946-8   [Google Scholar]