Volume 5, Issue 5 (May 2018), Pages: 40-42

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 Original Research Paper

 Title: Adaptive-delay based reconfigurable asynchronous pipeline

 Author(s): Adnan Ghafoor ^1, *, Arbab A. Khan ²

 Affiliation(s):

 ¹Department of Electrical Engineering, International Islamic University, Islamabad, Pakistan
 ²Department of Electrical Engineering, Capital University of Science and Technology, Islamabad, Pakistan

 https://doi.org/10.21833/ijaas.2018.05.005

 Full Text - PDF          XML

 Abstract:

This paper presents the asynchronous pipeline model implementable on FPGA platforms. The proposed event-controlled register acts as true adaptive delay element which adaptively prolongs the process of latching of data to store only the valid results, unlike other asynchronous approaches. Bundle data strategy with two-phase handshake protocol is used. In order to ensure the validity of the proposed pipeline, a fourth-order FIR filter was implemented on Xc7a100t-1csg324 FPGA. It was observed that the asynchronous pipeline implemented using auto place and route tools, adapts the delays of the data path and exhibits smooth functionality, with throughput supremacy over its synchronous counterpart. 

 © 2018 The Authors. Published by IASE.

 This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

 Keywords: Asynchronous, Adaptive delay, Pipeline, FPGA

 Article History: Received 27 November 2017, Received in revised form 29 February 2018, Accepted 3 March 2018

 Digital Object Identifier: 

 https://doi.org/10.21833/ijaas.2018.05.005

 Citation:

 Ghafoor A and Khan AA (2018). Adaptive-delay based reconfigurable asynchronous pipeline. International Journal of Advanced and Applied Sciences, 5(5): 40-42

 Permanent Link:

 http://www.science-gate.com/IJAAS/2018/V5I5/Ghafoor.html

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